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ds030100-u006a - 1 - an221e04 datasheet dynamically reconfigurable fpaa with enhanced i/o www.anadigm.com
ds030100-u006a - 2 - disclaimer anadigm reserves the right to make any changes without further notice to any products herein. anadigm makes no warranty, representation or guarantee r egarding the suitability of its products for any particular purpose, nor does anadigm assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including with out limitation consequ ential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. anadigm does not in this document convey any license under its patent rights nor the rights of others. anadigm software and a ssociated products cannot be used except strictly in accordance with an anadigm software license. the terms of the appropriate anadigm software license shall prevail over the above terms to the extent of any inconsistency. ? anadigm ? ltd. 2003 ? anadigm ? , inc. 2003 all rights reserved.
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 3 - product and architecture overview the an221e04 device consists of a 2x2 matrix of fully configurable analog blocks (cabs), surrounded by a fabric of programmable interconnect resour ces. configuration data is stored in an on-chip sram c onfiguration memory. compared with the first-generation fpaas, the anadigmvortex architecture provides a significantly improved signal-to-noise ratio as well as higher bandwidth. these devices also accommodate nonlinear functions such as sensor response linearization and arbitrary waveform synthesis. the an221e04 device features an advanced input/output structure that allows the fpaa to be programmed with up to six outputs ? or triple the number provided by the anx20e04 devices. the an221e04 devices have four configurable i/o cells and two dedicated output cells. for i/o-intensive applications, this means a single fpaa can now be used to process multiple channels of analog signals where two or more such devices were previously needed. in addition, the an221e04 devices allow designers to implement an integrated 8-bit analog-to-digital converter on the fpaa, eliminating the potential need for an external converter. using this new device, designers can route the digital output of the a/d converter off-chip using one of the dedicated output cells. figure 1: architectural overview of the an221e04 device with dynamic reconfigurabilit y, the functionality of the an221e04 can be reconfigured in-system by the designer or on-the-fly by a microprocessor. a single an221e04 can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to maintain precision operation despite system degradation and aging. product features ? dynamic reconfiguration ? four configurable i/o cells, two dedicated output cells ? 8-bit sar analog?to?digital converter ? fully differential architecture ? fully differential i/o buffering with options for single ended to differential conversion ? low input offset through chopper stabilized amplifiers ? 256 byte look-up table (lut) for linearization and arbitrary signal generation ? 4:1 input multiplexer ? typical signal bandwidth: dc-2mhz (bandwidth is cam dependent) ? signal to noise ratio: o broadband 80db o narrowband (audio) 100db ? total harmonic distortion (thd): 80db ? dc offset <100v ? package: 44-pin qfp (10x10x2mm) o lead pitch 0.8mm ? supply voltage: 5v ordering codes an221e04-qfpsp dynamically reconfigurable fpaa sample pack an221e04-qfpty dynamically reconfigurable fpaa tray (96 pcs) an221e04-qfptr dynamically reconfigurable fpaa tape & reel (1000 pcs) an221d04-eval an221e04 evaluation kit AN221D04-DEVLP an221e04 development kit applications ? real-time software control of analog system peripherals ? intelligent sensors ? adaptive filtering and control ? adaptive dsp front-end ? adaptive industrial control and automation ? self-calibrating systems ? compensation for aging of system components ? dynamic recalibration of remote systems ? ultra-low frequency signal conditioning ? custom analog signal processing [ for more detailed information on the features of the an221e04 device, please refer to the an121e04/an221e04 user manual ]
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 4 - electrical characteristics absolute maximum ratings parameter symbol min typ max unit comment dc power supplies avdd(2) bvdd dvdd -0.5 - 5.5 v v avss, bvss, dvss and svss all held to 0.0 v a xvdd to xvdd offset -0.5 0.5 v ideally all supplies should be at the same voltage package power dissipation pmax 25c pmax 85c - - 1.8 0.73 w still air, no heatsink, 4 layer board, 44 pins. ja = 55c/w analog and digital input voltage vinmax vss-0.5 - vdd+0.5 v ambient operating temperature top -40 - 85 c storage temperature tstg -65 150 c a absolute maximum dc power supply rating - the failure mode is non- catastrophic for vdd of up to 7 volts, but will cause reduce d operating life time. the additional stress caused by higher local elec tric fields within the cmos circuitry may induce metal mi gration, oxide leakage and other time/quality related issues. recommended operating conditions parameter symbol min typ max unit comment dc power supplies avdd(2) bvdd dvdd 4.75 5.00 5.25 v avss, bvss, dvss and svss all held to 0 v analog input voltage. vina vmr-1.9 - vmr+1.9 v vmr is 2.0 volts above avss digital input voltage vind 0 - dvdd v junction temp tj -40 - 125 c assume a package ja = 55c/w b b in order to calculate the junction temper ature you must first empirically determine the current draw (total idd) for the desig n. once the current consumption established then the following formula can be used; tj = ta + idd x vdd x 55 c/w, where ta is the ambient temperature. the worst case ja of 55 c/w assumes no air flow an d no additional heatsink of any type. general digital i/o characteristics (vdd = 5v +/- 10%, -40 to 85 deg.c) parameter symbol min typ max unit comment input voltage low vih 0 - 30 - % of dvdd input voltage high vil 70 - 100 - % of dvdd output voltage low vol 0 - 20 - % of dvdd output voltage high voh 80 - 100 - % of dvdd input leakage current iil - - 1.0 a all pins except dclk input leakage current iil - 12.0 - a dclk if a crystal is connected and the on-chip oscillator is used max. capacitive load cmax - - 10 pf the maximum load for a digital output is 10 pf // 10 kohm min. resistive load rmin 10 - - kohm the maximum load for a digital output is 10 pf // 10 kohm dclk frequency fmax - - 40 mhz for mode = 1, max dclk is 16 mhz aclk frequency fmax - - 40 mhz divide down to <8 mhz prior to use as a cab clock clock duty cycle - 45 - 55 % all clocks
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 5 - detailed digital i/o interface ch aracteristics: vdd = 5.0volts lccb parameter symbol min typ max unit comment output voltage low vol vss - 150 mv load 20pf//50kohm to vss output voltage high voh 4.5 - vdd v load 20pf//50kohm to vss max. capacitive load cmax - - 20 pf maximum load 20 pf // 50 kohm min. resistive load rmin 50 - - kohm maximum load 20 pf // 50 kohm current sink isnkmax - - 15 ma lccb pin shorted to vdd current source isrcmax - - 4 ma lccb pin shorted to vss cfgflg, activate parameter symbol min typ max unit comment input voltage low vil 0 30 % % of dvdd input voltage high vih 70 100 % % of dvdd output voltage low vol vss - 85 mv pin load = internal pullup + 20pf//50k to vss output voltage high voh 4.5 - vdd v pin load = internal pullup + 20pf//50k to vss output voltage low vol vss - 200 mv pin load = external 5k ohm pullup + 20pf//50k to vss output voltage high voh 4.5 - vdd v pin load = external 5kohm pullup + 20pf//50k to vss max. capacitive load cmax - - 50 pf maximum load 50 pf // 50 kohm min. resistive load rmin 50 - - kohm maximum load 50 pf // 50 kohm current sink isnkmax - - 2.5 ma pin shorted to vdd current source isrcmax - - 200 a pin shorted to vss external resistive pullup rpullupext 5 7.5 10 kohm use only if internal pullup is deselected errb parameter symbol min typ max unit comment input voltage low vil 0 30 % % of dvdd input voltage high vih 70 100 % % of dvdd output voltage low vol vss - 50 mv output voltage high voh 4.9 - vdd v max. capacitive load cmax - - 50 pf maximum load 50 pf // 50 kohm min. resistive load rmin 50 - - kohm maximum load 50 pf // 50 kohm current sink isnkmax - - 10 ma current source isrcmax - - 0 a external resistive pullup rpullupext 10 10 10 kohm dclk,mode,din,execut e,porb,cs1b,cs2b parameter symbol min typ max unit comment input voltage low vil 0 - 30 % % of dvdd input voltage high vih 70 - 100 % % of dvdd
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 6 - outclk/spimem,doutclk parameter symbol min typ max unit comment output voltage low vol 0 - 20 % % of dvdd output voltage high voh 80 - 100 % % of dvdd max. capacitive load cmax - - 50 pf maximum load 50 pf // 50 kohm min. resistive load rmin 10 - - kohm maximum load 50 pf // 50 kohm current sink isnkmax - - 17 ma current source isrcmax - - 4 ma aclk/spip parameter symbol min typ max unit comment input voltage low vil 0 - 30 % % of dvdd input voltage high vih 70 - 100 % % of dvdd output voltage low vol 0 - 20 % % of dvdd output voltage high voh 80 - 100 % % of dvdd max. capacitive load cmax - - 50 pf maximum load 50 pf // 50 kohm min. resistive load rmin 10 - - kohm maximum load 50 pf // 50 kohm current sink isnkmax - - 15 ma current source isrcmax - - 4 ma
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 7 - analog inputs general parameter symbol min typ max unit comment high precision input range c vina 0.5 - 3.5 v vmr +/- 1.5v standard precision input range d vina 0.1 - 3.9 v vmr +/- 1.9v high precision differential input c vdiffina 0 - +/-3.0 v common mode voltage = 2 v standard precision differential input d vdiffina 0 - +/-3.8 v common mode voltage = 2 v common mode input range vcm 1.8 2.0 2.2 v input offset vos - 5 15 mv non-chopper stabilized input input frequency fain 0 <2 8 mhz max value is clock, cam and input stage dependant. input frequency is limited to approx <2mhz due to cam signal processing which is based on sampled data architectures. c. high precision operating range provides optimal linearity and dynamic range. d. standard precision operating range provides maximum dynamic range and reduced linearity. input differential amplifier on and filter off parameter symbol min typ max unit comment input range vina vdiffina see analog input above usable input range will be reduced by the effective gain setting gain setting ginamp 16 - 128 gain accuracy - 1.0 2.5 % gain drift (temperature, supply voltage zand time) dist - - 1.0 % equivalent input offset voltage vos - 3 12 mv non-chopper stabilized input when the input amplifier and filter are used in combination vos contribution comes only from the input amplifier offset voltage temperature coefficient voffsettc - 1 10 v/c from -40c to 125c input frequency c fain 0 - 2 mhz input frequency d fain 0 <2 8 mhz power supply rejection ratio psrr 65 - - db d.c. amp gain =16 a.c. see graphs page 18 common mode rejection ratio cmrr - 67 - db large signal harmonic distortion dist - -65 - db 0.4v p-p differential input at 660hz gain setting = 16 input resistance rin 10 - mohm input capacitance cin - 5.0 pf input referred noise figure nf - 0.1 - v/sqrthz input cell gain = 16 applies to audio frequency range (400hz to 30khz). see graphical data on page 18 signal-to noise ratio and distortion sinad - 75 - db input signal = 285 mv p-p diff, audio frequency range see graphical data on page 18 spurious free dynamic range sfdr - 73 - db input signal = 100 mv p-p diff see graphical data on page 18 c. high precision operating range provides optimal linearity and dynamic range. d. standard precision operating range provides maximum dynamic range and reduced linearity.
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 8 - input differential chopper amplifier on and filter off parameter symbol min typ max unit comment input range vina vdiffina see analog input above usable input range will be reduced by the effective gain setting gain setting ginamp 16 - 128 gain accuracy - 1.0 2.5 % gain drift, (temperature, supply voltage and time) - - 1.0 % chopper frequency clock range fch fc/260100 - >250 khz fc = master clock frequency set fch as slow as possible fch > 250khz will result in some signal attenuation equivalent input offset voltage vos - <100 200 v chopper stabilized amplifier the maximum value of 200v is guaranteed by production test this is a tester limitation offset voltage temperature coefficient voffsettc - 0.5 2.0 v/c from -40c to 125c power supply rejection ratio psrr 65 - - db d.c. a.c. see graphs on page 18 common mode rejection ratio cmrr - 102 - db large signal harmonic distortion dist - -40 - db 0.4v p-p differential input at 660hz gain setting = 16 input frequency fain 0 fch/20 fch/2 khz fch=chopper clock frequency the chopper frequency and input frequency should be chosen such that subsequent low pass filtering can remove the chopper stage frequency elements input resistance rin 10 - mohm input to filter or chopper input capacitance cin - 5.0 pf input referred noise figure nf - 0.09 - v/sqrthz input cell gain = 16 applies to audio frequency range chopper clock fch = 250khz see graphical data on page 18 signal-to noise ratio and distortion sinad - 75 - db input signal = 285 mv p-p differential, audio frequency range see graphical data on page 18 spurious free dynamic range sfdr - 74 - db input signal =100 mv p-p differential see graphical data on page 18 input differential amplifier off and filter on parameter symbol min typ max unit comment input range vina vdiffina see analog input above equivalent input offset vos - 8 32 mv non-chopper stabilized input, filter corner frequency =470khz offset voltage temperature coefficient voffsettc - 0.05 i 1.0 ii mv/c from -40c to 125c i. measured at filter corner=470khz ii. maximum at filter corner=76khz input frequency fain - - - mhz input filter frequenc y will define the maximum frequency input filter is recommended to be >30x higher than the max input frequency, for 80db distortion performance
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 9 - common mode rejection ration cmrr - 60 - db power supply rejection ratio psrr 68 - - db d.c. a.c. see graphical data on page 19 large signal harmonic distortion dist - -82 - db 4v p-p differential input at 660hz filter corner frequency 470khz input low pass filt er (anti-alias) corner frequency settings ffiltcorner 76 - 470 khz input resistance rin 10 - - mohm input to filter or chopper input capacitance cin - 5.0 pf input referred noise figure nf - 0.17 - v/sqrthz input cell filter corner fc = 470khz applies to audio frequency range see graphical data on page 18 signal-to noise ratio and distortion sinad - 84 - db input signal = 1400 mv p-p diff, audio frequency range see graphical data on page 18 spurious free dynamic range sfdr - 90 - db input signal =1400 mv p-p differential see graphical data on page 18 input differential voltage mode, amplifier off, filter off and unity gain stage on parameter symbol min typ max unit comment input range vina vdiffina see analog input above v equivalent input offset vos - 5 15 mv non-chopper stabilized input offset voltage temperature coefficient voffsettc - 20 50 v/c from -40c to 125c input frequency fain - - 1.0 mhz gain bandwidth limited by input impedance power supply rejection ratio psrr 60 - - db d.c. a.c. see graphs on page 18 common mode rejection ratio cmrr - 60 - db large signal harmonic distortion dist - -80 - db 4v p-p differential input at 660hz large signal harmonic distortion dist - -80 - db 3v p-p single ended signal at 660hz input resistance rin - 126 - kohm input to unity gain stage input capacitance cin - 2.0 5.0 pf input referred noise figure nf - 0.16 - v/sqrthz applies to audio frequency range see graphical data on page 18 signal-to noise ratio and distortion sinad - 84 - db input signal = 1400 mv p-p diff, audio frequency range see graphical data on page 18 spurious free dynamic range sfdr - 90 - db input signal =1400 mv p-p differential see graphical data on page 18 input differential voltage mode, amplifier o ff, filter off and unity gain stage off parameter symbol min typ max unit comment input range vina vdiffina see analog input above v equivalent input offset vos n/ a n/a n/a mv see cam op amp offset voltage temperature coefficient voffsettc n/a n/a n/a v/c see cam op amp. from -40c to 125c input frequency fain - - 8 mhz dependant upon cam power supply rejection ratio psrr n/a n/a n/a db see cam op amp large signal harmonic distortion dist - -85 - db see cam op amp input resistance rin - - - mohm input to cam directly (input cell bypass mode). this variable is influenced by cab capacitor size, cab clock frequency and cab architecture input capacitance cin - - - pf input to cam directly (input cell bypass mode) this variable is influenced by cab capacitor size, cab clock frequency and cab architecture
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 10 - analog outputs (see ?output cell? section in the an120e04/an220e04 user manual for more details) parameter symbol min typ max unit comment high precision output range c vouta 0.5 - 3.5 v vmr +/- 1.5v standard precision output range d vouta 0.1 - 3.9 v vmr +/- 1.9v high precision differential output c vdiffouta - - +/-3.0 v common mode voltage = 2 v standard precision differential output d vdiffouta - - +/-3.8 v common mode voltage = 2 v common mode voltage vcm 1.9 2.0 2.1 v c . high precision operating range provides optimal linearity and dynamic range. d . standard precision operating range provides maximum dynamic range and reduced linearity. output voltage mode and filter on, corner frequency 470khz parameter symbol min typ max unit comment input range vina vdiffina see analog input above v equivalent input offset vos - 5 15 mv offset voltage temperature coefficient voffsettc 0.05 i 1.0 ii mv/c from -40c to 125c i measured at filter corner: 470khz ii maximum at filter corner: 76khz output frequency faout - - - mhz output filter frequency will define the maximum frequency input filter is recommended to be >30x higher then the max input frequency, for good distortion performance power supply rejection ratio psrr 60 - - db d.c. a.c. see graphical data on page 19 large signal harmonic distortion dist - -82 - db 4v p-p differential input at 660hz filter corner frequency 470khz input low pass filt er (anti-alias) corner frequency settings ffiltcorner 76 - 470 khz output load c e rload 0.1 - - mohm output load c e cload - - 50 pf output load d e rload 1 10 - kohm additional loading causes internal voltage drops across output stage and series resistances the output stage has a small signal output impedance of approx 10ohm output load d e cload - - 100 pf common mode rejection ratio cmrr - 56 - db input referred noise figure nf - 0.22 - v/sqrthz output filter corner fc = 470khz applies to audio frequency range see graphical data on page 18 signal-to noise ratio and distortion sinad - 82 - db input signal = 1400 mv p-p diff, audio frequency range see graphical data on page 18 spurious free dynamic range sfdr - 90 - db input signal =1400 mv p-p diff see graphical data on page 18 c . high precision operating range provides optimal linearity and dynamic range. d . standard precision operating range provides maximum dynamic range and reduced linearity. e . the maximum load for an analog output is 50 pf // 100 kohms. this load maybe with respect to analog ground vmr or avss.
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 11 - output voltage mode and filter off (bypass mode) parameter symbol min typ max unit comment input range vina vdiffina see analog input above v equivalent input offset vos n/ a n/a n/a mv see cam op amp offset voltage temperature coefficient voffsettc n/a n/a n/a mv/c see cam op amp output frequency c e faout - - 4 mhz output frequency d f faout - - 8 mhz the realizable output frequency is limited to approx <2mhz due to cam signal processing which is based on sampled data architectures. power supply rejection ratio psrr n/a n/a n/a db see cam op amp large signal harmonic distortion dist - -85 - db output load rload n/a n/a n/a mohm see cam op amp output load cload n/a n/a n/a pf see cam op amp c . high precision operating r ange provides optimal linearity and dynamic range. d . standard precision operating range provides maximum dynamic range and reduced linearity. e . the maximum load for an analog output is 50 pf // 100 kohms. this load maybe with respect to analog ground vmr or avss. f . the maximum load for an analog output is 100 pf // 100 kohms. th is load must be differential and with respect to analog groun d(vmr). vmr (voltage mid rail) and vref (reference voltage) ratings parameter symbol min typ max unit comment vmr output voltage vvmr 1.925 2.01 2.075 v at 25c, vdd=5.00 volts vref+ output voltage vref+ 3.4 3.51 3.6 v at 25c, vdd=5.00 volts vref- output voltage vref- 0.45 0. 505 0.55 v at 25c, vdd=5.00 volts output voltage deviation vref+, vmr, vref- vrefout - 0.5 1 % over process and supply voltage corners voltage temperature coefficient vref+, vmr, vref- vreftc - - - - see typical graphical data below -40c to 125c f power supply rejection ratio, vmr pssr 60 - - db power supply rejection ratio vref+ and vref- pssr 75 - - db start up time tstart - - 1 ms assuming recommended capacitors v+ref vs temperature 3.490 3.495 3.500 3.505 3.510 -50 0 50 100 150 tchip (c) volts vmr vs temperature 1.990 1.995 2.000 2.005 2.010 -50 0 50 100 150 tchip (c) volts vref- vs temperature 0.490 0.495 0.500 0.505 0.510 -50 0 50 100 150 tchip (c) volts
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 12 - cab (configurable analog block) differential operational amplifier parameter symbol min typ max unit comment high precision input/output range c vinouta 0.5 - 3.5 v vmr +/- 1.5v standard precision input/output range d vinouta 0.1 - 3.9 v vmr +/-1.9v high precision. differential input/output c vdiffioa - - +/-3.0 v common mode voltage = 2 v standard precision differential input/output d vdiffioa - - +/-3.8 v common mode voltage = 2 v common mode input voltage range d vcm 0 2.0 4 v common mode output voltage range vcm 1.9 2.0 2.1 v equivalent input voltage offset. voffset 0.1 5 15 mv some cams (configurable analog modules) can inherently compensate offset voltage temperature coefficient voffsettc - 1 10 v/c from -40c to 125c some cams (configurable analog modules) can inherently compensate power supply rejection ratio pssr - 80 - db variation between cams is expected because of variations in architecture common mode rejection ratio cmrr - 77 - db example 1 gaininv cam cam clock = 1mhz cam parameter settings gain = 1 common mode rejection ratio cmrr - 60 - db example 2 filterbiquad setting = low pass filter cam clock = 1mhz cam parameter settings gain = 1, corner frequency = 50khz quality factor = 0.707 differential slew rate, internal slew - 50 - v/sec applicable when the opamp load is internal to the fpaa differential slew rate, external slew - 10 - v/sec applicable when the opamp driving signal out of the fpaa package unity gain bandwidth, full power mode. ugb - 50 - mhz applicable when sourcing and loading the opamp with a load internal to the fpaa input impedance, internal rin 10 - - mohm output impedance, internal rout - - - ohms the opamp output is designed to drive all internal nodes, these are dominantly capacitive loads output impedance, external rout - - - ohms output to an fpaa output pin (ouput cell bypass mode). this variable is influenced by cab capacitor size, cab clock frequency and cab architecture output load, external c e rload 0.1 - - mohm output load, external c e cload - - 50 pf output load, external d e f rload 1 10 - kohm additional loading causes internal voltage drops across output stage and series resistances the output stage has a small signal output impedance of approx 10ohm output load, external d e f cload - - 50 pf noise figure g noise - 0.13 - v/sqrthz example1 gaininv cam cam clock = 1mhz gain = 1
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 13 - signal-to noise ratio and distortion g sinad - 80 - db input signal=1400 mv p-p differential audio frequency range example. gaininv cam cam clock = 1mhz gain = 1 spurious free dynamic range g sfdr - 92 - db input signal=1400 mv p-p differential, audio frequency range example. gaininv cam cam clock = 1mhz gain = 1 c . high precision operating range provides optimal linearity and dynamic range. d . standard precision operating range provides maximum dynamic range and reduced linearity. e . the maximum load for an analog output is 50 pf || 100 kohms. this load may be with respect to analog ground vmr or avss. f . using the fpaa with cab op amp?s driving directly off-chip, requires care, full characterizati on of the performance of each a pplication circuit by the circuit designer is necessary. g . this specification parameter can only be characterized when a circui t topology is configured onto the cab differential amplif ier architecture. the figure provided here is an representative on the performanc e of one specific cam, as specified in the comments. the idealized open loop gain plot is provided for information only. this information is associated with the fpaa in full power mode of operation. the fpaa operation amplifier open loop gain cannot be observed nor used when associated with external connections to the device. internal reprogr ammable routing impedances and switched capacitor circuit architecture using this operational amplifier limit the effective usable bandwidth of a circuit realized in the fpaa to less than 2mhz. idealized cab op am p, open loop gain [db] -20 -10 0 10 20 30 40 50 60 70 80 90 0.1 10 1000 100000 frequency (khz) open loop gain (db)
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 14 - cab (configurable analog block) differential comparator parameter symbol min typ max unit comment input range, internal vina 0.1 - 3.9 v input range, external vina 0.0 - vdd v differential input, internal vdiffina - - +/-3.8 v common mode voltage = 2 v differential input, external vdiffina +/- 0.0 - +/- vdd v common mode output voltage range, internal c vcm 1.9 2.0 2.1 v common mode input voltage range, external c vcm 0 2.0 4 v common mode input voltage, external d vcm 0 - 5 v the comparator will function correctly differential output voutdiff - - +/-5 v single pin output (ox1p) vout 0 - 5 v input voltage offset voffcomp - 2 10 mv zero hysterisis offset voltage temperature coefficient voffsettc - 1 10 v/c from -40c to 125c, zero hysterisis setup time, internal tsetint - - 125 nsec setup time, external tsetext - - 500 nsec delay time tdelay ?td+25 - 1?td+25 nsec td = 1/fc fc = master clock frequency output load rload 10 - - kohm applies if comparator drive off chip with output cell in bypass mode output load cload - - 50 pf applies if comparator drive off chip with output cell in bypass mode differential variable reference voltage settings compvref 0 - +/-4.0 v differential hysteresis hysta1 - voffcomp - mv hysteresis setting = zero differential hysteresis hysta2 - 20 - mv hysteresis setting = 10mv differential hysteresis hysta3 - 40 - mv hysteresis setting = 20mv differential hysteresis hysta4 - 80 - mv hysteresis setting = 40mv hysteresis setting accuracy hystb - 25 - % hysteresis temperature coefficient hysttc1 - 5 - v/c hysteresis setting = zero hysteresis temperature coefficient hysttc2 - 50 - v/c hysteresis setting = 10mv hysteresis temperature coefficient hysttc3 - 100 - v/c hysteresis setting = 20mv hysteresis temperature coefficient hysttc4 - 200 - v/c hysteresis setting = 40mv c . high precision operating range provides optimal linearity and dynamic range. d . standard precision operating range provides maximum dynamic range and reduced linearity.
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 15 - esd characteristics pin type human body model machine model charged device model digital inputs 4000v 250v 4kv digital outputs 4000v 250v 4kv digital bidirectional 4000v 250v 4kv digital open drain 4000v 250v 4kv analog inputs 2000v 200v 4kv analog outputs 1500v 100v 4kv reference voltages 1500v 100v 4kv the an221e04 is an esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000v readily accumulate on the human body and test equipment and can discharge without detection. although the an221e04 device features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. power consumption ? low power mode parameter symbol min typ max unit comment minimum power 1a idd - 0.2 - ma vdd=5.00 volts, tj=25c nominal 25% power 1b idd - 25 30 ma vdd=5.00 volts, tj=25c nominal 50% power 1c idd - 42 47 ma vdd=5.00 volts, tj=25c nominal 75% power 1d idd - 50 55 ma vdd=5.00 volts, tj=25c maximum power 1e idd - 60 63 66 - 68 - ma vdd=4.75 volts, tj=85c vdd=5.00 volts, tj=25c vdd=5.25 volts, tj= -40c temperature coefficient - - -2 -10 a/c 1a. external clock, all analog f unction disabled, memory active. 1b fpaa active elements ? two core op-amps (low power mode), one comparator, one input (bypass mode), one output filter and differential to single-ended converter (low power mode). 1c. fpaa active elements ? four core op-amps (low power mode), two comparators (one using sar), two inputs (bypass mode), two out put filters and two differential to single- ended converters (low power mode). 1d fpaa active elements ? six core op-amps (low power mode), three comparators (two using sar), three inputs (bypass mode, two output filters and two differential to single-ended converters (low power mode). 1e fpaa active elements ? eight core op-amps (low power mode), four comparators (two using sar), four inputs (bypass mode), two output filters and two differential to single- ended converters (low power mode). power consumption ? full power mode parameter symbol min typ max unit comment full power mode minimum power 2a idd - 1.5 - ma vdd=5.00 volts, tj=25c full power mode nominal 25% power 2b idd - 80 90 ma vdd=5.00 volts, tj=25c full power mode nominal 50% power 2c idd - 150 160 ma vdd=5.00 volts, tj=25c full power mode nominal 75% power 2d idd - 170 190 ma vdd=5.00 volts, tj=25c full power mode maximum power 2e idd - 200 210 220 - 230 - ma vdd=4.75 volts, tj=85c vdd=5.00 volts, tj=25c vdd=5.25 volts, tj= -40c 2a. an220e04 crystal oscillator, all anal og functions disabled, memory active. 2b. fpaa active elements ? two core op-amps , one comparator, one input filter and chopper amplifier, one output filter and differential to single-ended converter. 2c. fpaa active elements ? four core op-amps , two comparators (one using sar), two input filters and two chopper amplifiers, two output filters and two differential to single-ended converters. 2d fpaa active elements ? six core op-amps, thr ee comparators (two using sar), three input filters and three chopper amplifiers, two output filters and two differential to single-ended converters. 2e fpaa active elements ? eight core op-amps, f our comparators (two using sar), four input filters and two chopper amplifiers, two output filters and two differential to single-ended converters. power consumption low power mode (temp 25 degree c) 0 10 20 30 40 50 60 70 25% 50% 75% 100% resource utilization idd (ma) vdd=4.75v vdd=5.0v vdd=5.25v power consumption full power mode (temp 25 degree c) 0 50 100 150 200 250 25% 50% 75% 100% resource utilization idd (ma) vdd=4.75v vdd=5.0v vdd=5.25v
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 16 - pinout pin numb er pin name pin type comments 1 i4pa analog in+ 2 i4na analog in- 3 o1p analog out+ 4 o1n analog out- 5 avss analog vss 6 avdd analog vdd 7 o2p analog out 8 o2n analog out 9 i1p analog in+ 10 i1n analog in- 11 i2p analog in+ 12 i2n analog in- 13 shield analog vdd low noise vdd bias for capacitor array n-wells 14 avdd2 analog vdd analog power 15 vrefmc vref attach filter capaci tor for vref- 16 vrefpc vref attach filter capacitor for vref+ 17 vmrc vref attach filter capacitor for vmr (voltage main reference) 18 bvdd analog vdd analog power for bandgap vref generators 19 bvss analog vss analog ground for bandgap vref generators digital in in multi-device systems... 0, ignore incoming data (unless currently addressed) 1, pay attention to incoming data (watching for address) 20 cfgflgb digital out 0, device is being configured z, device is not being configured (if internal pullup is selected) 21 cs2b digital in 0, chip is selected 1, chip is not selected digital in (during config) 0, allow configuration to proceed 1, hold off configuration 22 cs1b digital in (after config)_ passes read-back data through to lcc_b pin 23 dclk digital in 24 svss digital vss digital ground - substrate tie 25 mode digital in 0, synchronous serial interface 1, spi eprom interface digital in mode = 0, analog clock < 40 mhz 26 aclk / spip digital out mode = 1, spi eprom or serial eprom clock digital out during power-up, sources spi eprom initialization command string 27 outclk / spimem digital out after power-up, sources any of the four internal analog clocks 28 dvdd digital vdd 29 dvss digital vss 30 din digital in serial configuration data input 31 lccb digital out 1, local configuration is needed. once configuration is completed, it is a registered version of cs1b or if the device is addressed for r ead, it serves as serial data out port digital in (monitored out) 0, initiate reset 1, no action 32 errb digital out 0, error condition z, no error condition (external pullup required) 33 activate digital in 0, hold off completion of configuration rising edge, allow completion of configuration o.d. output 0, device has not yet completed primary configuration z, device has completed primary configur ation (if internal pullup is selected) digital out a buffered version of dclk. 34 doutclk / test digital in (factory reserved te st input. float if unused) 35 porb digital in 0, chip held in reset state rising edge, re-initiates power on reset sequence to initiate a por reset cycle, the minimum pulse width required on the porb pin is 25ns. 36 execute digital in 0, no action 1, transfer shadow ram into configuration ram 37 i3p analog in+ 38 i3n analog in- 39 i4pd analog in+ analog multiplexer input signals. the multiplexer can accept 4 differential inputs or 8 single ended inputs 40 i4nd analog in- 41 i4pc analog in+ 42 i4nc analog in- 43 i4pb analog in+ 44 i4nb analog in-
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 17 - mechanical and handling the an221e04 comes in the industry standard 44 lead qfp package. dry pack handling is recommended. the package is qualified to msl3 (jedec standard, j-std-020a, level 3). once the device is removed from dry pack, 30c at 60% humidity for not longer t han 168 hours is the maximum recommended exposure prior to solder reflow. if out of dry pack for longer than this recommended peri od of time, then the recommended bake out procedure prior to so lder reflow is 24 hours at 125c.
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 18 - distortion, sinad and snr measurements the following plots give an indication of the dist ortion, sinad and snr for some representative cams. input cel l ugb snr, dst n, sinad -100 -80 -60 -40 -20 0 20 40 60 80 10 0 12 0 0.7 1.4 2.8 5.6 7.0 input [vp-p] [db] snr[ db] sinad[ db] distn[ db] input cell low pass filter snr, dstn, sinad -100 -80 -60 -40 -20 0 20 40 60 80 10 0 12 0 0.7 1.4 2.8 5.6 7.0 input [vp-p] [db] snr[ db] sinad[ db] distn[ db] input cell amplifier snr,dstn,sinad measured with inputcell gain g = 16 same results for input amplifier and chopper amplifier stage, if the signal from the chopper amplifier is correctly filtered before measurement. -100.00 -80.00 -60.00 -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 10 0 . 0 0 0.08 0.14 0.21 0.28 0.35 0.42 0.49 input [vp-p] [db] snr[ db] sinad[ db] distn[ db] output cell snr, dstn, sinad -100 -80 -60 -40 -20 0 20 40 60 80 10 0 12 0 0.7 1.4 2.8 3 .5 5.6 7.0 input [vp-p] [db] snr[ db] si nad[ db] di st n[ db] gaininv cam snr, dstn, sinad this graph shows the typical performance of an fpaa cab when configured with a cam in this example gaininv cam input signal=1400 mv p-p differential, cam clock = 1mhz cam parameter settings gain = 1 -120 -100 -80 -60 -40 -20 0 20 40 60 80 10 0 0.7 1.4 2.8 3.5 5.6 7.0 input [vp-p] [db] snr[ db] sinad[ db] distn[ db]
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 19 - power supply rejection ratio (psrr) measurements the following plots give an indication of the psrr for some representative cams. avdd to power supply (ps): 5v +/- 0.25v sinusoidal waveform (100 khz to 1 mhz) input am p psrr [db] 20.00 30.00 40.00 50 .0 0 60.00 70 .0 0 80.00 d c 10 0 1k hz 10 k hz 10 0 k hz 1m hz input lpf psrr [db] 20.00 30.00 40.00 50 .0 0 60.00 70 .0 0 80.00 d c 15 5 0 10 0 1k hz 10 k hz 10 0 k hz 1m hz vmr, vref+, vref- psrr [db] 20.00 30.00 40.00 50 .0 0 60.00 70 .0 0 80.00 90.00 100.00 d c 10 0 1k hz 10 k hz 10 0 k hz 1m hz psrr_vmr [db] psrr_vrefp [ db] psrr_vrefp [ db] output voltage mode + lpf psrr [db] 20.00 30.00 40.00 50 .0 0 60.00 70 .0 0 80.00 d c 10 0 1khz 10 khz 10 0 khz 1m hz gaininv _1m hz psrr [ d b] 20 30 40 50 60 70 80 90 10 0 d c 5 0 10 0 1k hz 10 k hz 10 0 k hz 1m hz gaininv_4mhz psrr [db] 20 30 40 50 60 70 80 90 10 0 10 0 1k hz 10 k hz 10 0 k hz 1m hz
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 20 - the following is provided for information only, as and when additional characterization data is collected ?noise measurements? will be added formally to the datasheet. noise and distortion observations the following plots give an indication of the noise characteristics of anadigm ? ?s an221e04 fpaa device. these were done using a simple set-up and in many cases reflec t the noise limit of the setup. actual device noise margins are expected to be better. signal and noise for the input cell (input signal - 50mvp-p differential to the fpaa at 10 khz) signal and noise for the output cell (wit h a differential input 4v p-p, 660hz) input gain stage set at x16 input anti-aliasing filter set off input chopper amplifier set off si g nal to noise: -92 db , at 376khz , 3hz bw signal to noise: - 106 db, at 345khz, 3hz bw voltage output mode (including filter) on output smoothing filter set at f c = 470 khz
an221e04 datasheet ? dynamically reco nfigurable fpaa with enhanced i/o ds030100-u006a - 21 - measured thd for input and output cells (w ith a differential input 4v p-p, 660hz) settings distortion in db input cell with anti-alia sing filter set at f c = 470 khz 81.6 output cell with differential to single ended converter and output smoothing filter set at f c = 470 khz 82 signal and noise for a representative cam ? gaininv ca m (input signal of 700mv p-p differential at 10 khz) si g nal to noise: 108 db, at 528 khz, 3hz bw a s above, zoom to lower fre q uenc y thd for a representative cam ? gaininv cam (with a differential input 4v p-p, 660hz) cam clock frequency distortion (db) 250 khz 80.00 1 mhz 72.83 2 mhz 69.22 4 mhz 73.48

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